1. Technical Field
The present invention relates to a semiconductor memory apparatus, and more particularly, to a delay locked loop circuit for a semiconductor memory apparatus that is capable of preventing errors due to a transmission path of a delay locked loop clock from occurring.
2. Related Art
A delay locked loop (DLL) circuit generates delay locked loop clocks RCLKDLL and FCLKDLL to synchronize a phase of an external clock CLK supplied from the outside of a semiconductor memory apparatus and a phase of an internal clock iclk used inside the semiconductor memory apparatus.
The delay locked loop clock RCLKDLL is synchronized with a rising edge of the external clock CLK, and the delay locked loop clock FCLKDLL is synchronized with a falling edge of the external clock CLK.
As shown in FIG. 1, the delay locked loop clocks RCLKDLL and FCLKDLL, which are output by a delay locked loop circuit 10 for a semiconductor memory apparatus, pass through signal lines and are supplied to a first data input/output unit 11 and a second data input/output unit 12, respectively.
The first and second data input/output units 11 and 12 are constructed to process half of the input/output data by using the delay locked loop clocks RCLKDLL and FCLKDLL. For example, if the number of bits of all of the data that is output according to an input command or an output command is 16 bits, the first data input/output unit 11 processes 8 data bits that correspond to bit numbers 0 to 7 and the second data input/output unit 12 processes the remaining data.
As the semiconductor memory apparatus operates at a high speed and processes an increasing data load, the semiconductor memory apparatus generally uses a plurality of data input/output units so as to smoothly perform a data input/output operation.
The first and second data input/output units 11 and 12 perform delay and timing adjustment on the delay locked loop clocks RCLKDLL and FCLKDLL in accordance with time tAC required to access data from a point of time when a clock CLK is generated and column access strobe latency, in consideration of skews of the delay locked loop clocks RCLKDLL and FCLKDLL.
As shown in FIG. 2, the delay locked loop circuit 10 according to the related art includes a duty cycle correcting part 20 and a delay locked loop clock driving part 30.
The delay locked loop clock driving part 30 includes a phase dividing part 40, a first driver 50, and a second driver 60.
The operation of the delay locked loop circuit according to the related art that has the above-described structure will now be described.
The duty cycle correcting part 20 corrects and outputs duty cycles of internal clocks iRCLK and iFCLK that are delayed and locked by a delay loop (not shown) in the delay locked loop circuit 10.
The phase dividing part 40 of the delay locked loop clock driving part 30 divides a phase of the output DCCOUT of the duty cycle correcting part 20 and outputs phase dividing signals ROUT and FOUT.
The first driver 50 of the delay locked loop clock driving part 30 drives the phase dividing signal ROUT as the delay locked loop clock RCLKDLL and outputs it to a signal line outside the delay locked loop circuit 10.
The second driver 60 drives the phase dividing signal FOUT as the delay locked loop clock FCLKDLL and outputs it to a signal line outside the delay locked loop circuit 10.
In the semiconductor memory apparatus according to the related art, the delay locked loop clocks RCLKDLL and FCLKDLL have the above-described skews while being transmitted through the signal lines, as shown in FIG. 1.
The first and second data input/output units 11 and 12 shown in FIG. 1 correct the skews of the delay locked loop clocks RCLKDLL and FCLKDLL.
As shown in FIG. 1, in the semiconductor memory apparatus according to the related art, the signal lines that are connected to the first and second data input/output units 11 and 12 are asymmetrical. For this reason, it is not possible to correct the skews of the delay locked loop clocks RCLKDLL and FCLKDLL. As a result, the skews of the delay locked loop clocks RCLKDLL and FCLKDLL become worse.
The semiconductor memory apparatus causes a timing error because of the skews of the delay locked loop clocks RCLKDLL and FCLKDLL. In a normal case, the two delay locked loop clocks RCLKDLL and FCLKDLL do not overlap each other. However, as shown in FIG. 3, since the two delay locked loop clocks RCLKDLL and FCLKDLL overlap each other during an interval of “A”, the semiconductor memory apparatus causes a timing error.
In the case of a double data rate dynamic RAM (DDR RAM), the DDR RAM receives or outputs data at timings that are synchronized with rising and falling edges of the clocks. Accordingly, when the overlapping clock interval exists, such as during the interval “A” shown in FIG. 3, an excessive data input/output error may occur due to an erroneous operation performed by a data input/output structure.
The above-described problems in the related art occur due to the difference in a width of a high-level interval between the delay locked loop clocks RCLKDLL and FCLKDLL, as shown in FIG. 3. Therefore, it is not possible to resolve the problems in the related art by delaying either the delay locked loop clock RCLKDLL or the delay locked loop clock FCLKDLL. Further, to delay the delay locked loop clocks RCLKDLL and FCLKDLL causes another problem in that it is difficult for the first and second data input/output units to adjust the data access time tAC.